Bit errors and ADC testing

Most engineers are introduced to the basic performance parameters of analog/digital converters in school. So specifications such as SNR, SINAD (Signal-to-noise and distortion ratio), ENOB (Effective Number of Bits), and THDA (total harmonic distortion analysis) are all familiar ADC terms found in ADC data sheets. Ditto for an INL error, described as the deviation, in LSB or percent of full-scale range (FSR), of an actual transfer function from a straight line.

Less well-known is how to quantify ADC errors that affect the bit error rate (BER), a measure widely used to characterize data communications. The number of bit errors is generally defined to be the number of received bits of a data stream over a communication channel that have been garbled by noise, interference, distortion or bit synchronization errors. The BER is the number of bit errors per unit time. The bit error ratio (also BER) is the number of bit errors divided by the total number of transferred bits during a studied time interval and is often expressed as a percentage.

The BERT or bit error rate test is a testing method for digital communication circuits that uses predetermined stress patterns consisting of a sequence of logical ones and zeros generated by a test pattern generator. A generic BERT typically consists of a test pattern generator and a receiver that can be set to the same pattern. They can be used in pairs, with one at either end of a transmission link, or singularly at one end with a loopback at the remote end. In use, the number of errors, if any, are counted and presented as a ratio such as 1 in 1,000,000.

Unfortunately, ADCs contribute to the BER in ways that are not easily predictable. The noise of the ADC creates some uncertainty in the output, but more important for BER are large errors. They are random and so infrequent that an SNR test of the ADC will rarely detect them. These types of large errors also plagued a few of the early ADCs for video applications, and were given the name sparkle codes because of their appearance on a TV screen as small white dots or “sparkles” under certain test conditions. These errors have also been called rabbits or flyers.

Explanations of how the error codes arise often use the example of a simple flash converter. The comparators in a flash converter are latched comparators usually arranged in a master-slave configuration. If the input signal is in the center of the threshold of a particular comparator, that comparator will balance, and its output will take longer to reach a valid logic level after the application of the latch strobe than the outputs of its neighboring comparators which are being overdriven. This phenomenon is known as metastability and arises when a balanced comparator cannot reach a valid logic level in the time allowed for decoding. If simple binary decoding logic is used to decode the thermometer code, a metastable comparator output may result in a large output code error.

Analog Devices explains the problem using a simple three-bit flash converter. Assume the input signal is exactly at the threshold of Comparator four and random noise makes the comparator toggle between a “1” and a “0” output each time a latch strobe is applied. The corresponding binary output should be interpreted as either 011 or 100.

If, however, the comparator output is in a metastable state, the simple binary decoding logic may produce binary codes 000, 011, 100, or 111. The codes 000 and 111 represent a one-half scale departure from the expected codes.

The probability of errors due to metastability rises with the sampling rate because less time is available for a metastable comparator to settle. Various measures have been taken in flash converter designs to minimize the metastable state problem. Metastable state errors may also appear in successive approximation and subranging ADCs which make use of comparators as building blocks. The same concepts apply, although the magnitudes and locations of the errors may be different.

A test system used to test for BER in an ADC uses an analog input to the ADC consisting of a high-stability low-noise sinewave generator. The analog input level is set slightly greater than full-scale, and the frequency is such that there is always slightly less than 1 LSB change between samples. The test set uses a series of latches to acquire successive codes called A and B. A logic circuit determines the absolute difference between A and B. This difference is then compared to the error limit, chosen to allow for expected random noise spikes and ADC quantization errors.

Errors which cause the difference to be larger than the limit will increment the counters. The number of errors, E, are counted over a period of time, T. The error rate is then calculated as BER = E/2Tf_s. The factor of two is in the denominator because the hardware records a second error when the output returns to the correct code after making the initial error. The error counter therefore increments twice for each error. It should be noted that the same function can be accomplished in software if the ADC outputs are stored in a memory and analyzed by a computer program.

Establishing the BER of a well-behaved ADC is difficult and time-consuming. Single unit can sometimes run for days without an error. For example, tests at Analog Devices on a typical 8-bit flash converter operating at a sampling rate of 75 MSPS yield a BER of approximately 3.7×10^–12 (1 error per hour) with an error limit of 4 LSBs. Meaningful tests for longer periods of time require special attention to EMI/RFI effects (possibly requiring a shielded screen room), isolated power supplies, isolation from soldering irons with mechanical thermostats, isolation from other bench equipment, and so forth.