Siemens Digital Industries Software introduced Tessent AnalogTest software – an innovative solution that reduces pattern generation time for analog circuit tests from months to days. The solution enables testing of analog circuitry in integrated circuits (ICs) up to 100 times faster than traditional manual methods.
Analog circuit testing has traditionally been a labor-intensive endeavor, requiring prolonged test coding and expensive mixed-signal test equipment. Working in tandem with Siemens’ market-proven Tessent DefectSim technology, the new Tessent AnalogTest software helps to dramatically shorten test coding time for analog circuitry in ICs by automatically generating minimal-impact design-for-test (DFT) circuitry and digital test patterns for nearly any analog circuit block. The tests run in less than a millisecond on almost any tester, and defect coverage can be verified in simulation up to 1000x faster than specification-based tests.
The introduction of Tessent AnalogTest marks the first automated DFT solution for analog circuitry in ICs, delivering digital vectors for testing and computing test coverage efficiently before tape-out to silicon production. The solution leverages digital automated test equipment (ATE) for the development of analog circuitry for reduced costs and enhanced productivity compared to using more expensive mixed-signal testers. This acceleration allows IC designers to achieve and verify high (>90%) IEEE P2427-based defect coverage in a matter of hours for individual circuit blocks, setting new speed benchmarks and dramatically reducing time-to-market.
Long-time Tessent DefectSim customer, onsemi, has used Tessent AnalogTest for a taped-out design. Using this tool, onsemi was able to achieve greater than 95% analog defect coverage and better than 100x test time improvement compared to traditional test methods.
The software uniquely extends its structural test generation capabilities by producing simulation testbenches from specification-based tests, utilizing the intuitive high-level ICL and PDL test descriptions as specified by IEEE P1687.2, which is the analog extension of the widely used digital IJTAG standard. These tests can verify the analog test flow and defect coverage for algorithmic trimming, top-up parametric tests, or ISO 26262 functional safety metrics. Additionally, embedding the scan tests can further enhance these metrics.
Tessent AnalogTest is in use by early partners and will be generally available in December 2025.
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