Virtually all digital, analog and mixed-signal ICs are now done in CMOS due to the technology’s extremely low power consumption, small size and immunity to noise. Low power consumption arises from the use of a two-transistor configuration resulting in zero power consumption except during brief transitions.
Interestingly, the bulk of CMOS power dissipation arises because of capacitive effects during switching. Moreover, the capacitive loading on the outputs of CMOS chips accounts for an appreciable amount of the total power dissipation. The overall effect is that of current consumption rising almost linearly with rising operating frequency. So measurements of CMOS power dissipation often end up being measurements of capacitance. It may be worth exploring how this behavior actually arises.
First a quick review. The complementary-symmetry metal-oxide semiconductor field-effect transistor fabrication process uses complementary and symmetrical pairs of P-type and N-type MOSFETs. In CMOS circuits, all P-type metal-oxide semiconductor (PMOS) transistors have either an input from the voltage source or from another PMOS transistor. Also, NMOS transistors need an input from another NMOS or from ground. A PMOS transistor exhibits low resistance between source and drain when a low gate voltage is applied and high resistance when a high gate voltage is applied. In contrast, an NMOS transistor exhibits high resistance between source and drain when a low gate voltage is applied, and low resistance when a high gate voltage is applied. All this is because high or low gate voltage determines the channel dimensions and hence conductance.
CMOS circuits consume power in two ways, statically and dynamically. Static power consumption is that when the CMOS gate is not switching, i.e. in a steady state when all inputs are held at some valid logic level and the circuit is not in charging states. Static power consumption is low and results from leakage current. In contrast, dynamic power consumption arises when the CMOS gate changes state. In addition, charging and discharging a capacitive output load–common in logic circuits–further boosts dynamic power consumption.
Typically, all CMOS logic has a CMOS inverter in the input and output stage. If the input is at logic 0, the NMOS device is off and the PMOS device is on. The output voltage is VCC, or logic 1. Similarly, when the input is at logic 1, the associated NMOS device is biased on and the PMOS device is off. The output voltage is at ground, or logic 0. Thus one of the transistors is always off when the gate is in either of these logic states. Because no current flows into the gate terminal, and there is no dc current path from VCC to ground, the quiescent(steady-state) current is zero, hence, static power consumption (Pq) is zero.
However, there is a small amount of static power consumption due to reverse-bias leakage between diffused regions of the MOS transistors and the substrate. This leakage inside a device is often modeled as parasitic diodes of a CMOS inverter. The source-drain diffusion and N-well diffusion form parasitic diodes. The parasitic diodes are reverse biased, so only their leakage currents contribute to static power consumption. The leakage current Ilkg of the diode is described by Ilkg =is(eqV/kT-1) where is = reverse saturation current, V = diode voltage, k = Boltzmann’s constant (1.38 × 10–23 J/K), q = electronic charge (1.602 × 10–19 C), and T = temperature in °K.
Static power consumption is the product of the device leakage current and the supply voltage. Most CMOS data sheets specify an ICC maximum in the 10 to 40-mA range, encompassing total leakage current (current into a device) and other circuit features possibly requiring static current not considered in the simple inverter model.
The leakage current, along with the supply voltage, causes static power consumption in CMOS. This static power consumption PS can be calculated by PS = VCC×ICC where VCC = supply voltage and ICC = device current. Finally, Another source of static current is called ΔICC. This results when the input levels are not driven all the way to the rail so the input transistors don’t switch off completely.
Transient power consumption arises when the transistors switch from one logic state to another. It is a result of the current needed to charge the internal nodes (switching current) plus the through-current (current that flows from VCC to ground when the P-channel and N-channel transistors turn on briefly at the same time during the logic transition). The frequency at which the device switches, plus the rise and fall times of the input signal, as well as the internal nodes of the device, directly affect the duration of the current spike. For fast input transition rates, the through-current of the gate is negligible compared to the switching current. Consequently, the dynamic supply current is governed by the internal capacitance of the IC and the charge and discharge current of the load capacitance.
Transient power consumption PT can be calculated from PT = Cpd×VCC2 ×fI×NSW where fI= input signal frequency, NSW = number of bits switching, and Cpd= dynamic power-dissipation capacitance. In the case of single-bit switching, NSW = 1.
Dynamic supply current is high in CMOS circuits because most power is consumed in moving charges in the parasitic capacitor in the CMOS gates. As a result, the simplified model of a CMOS circuit consisting of several gates can be viewed as one large capacitor charged and discharged between the power-supply rails. Consequently, the power–dissipation capacitance Cpd is often specified as a measure of this equivalent capacitance and is used to approximate the dynamic power consumption. Cpd is defined as the internal equivalent capacitance of a device calculated by measuring operating current without load capacitance. Depending on the output switching capability, Cpd can be measured with no output switching (output disabled) or with any of the outputs switching (output enabled).
To extend this idea, CMOS circuits consume additional power in charging the external load capacitance of the CMOS circuits connected to their output. And the value of this external load rises with switching frequency. If all outputs have the same load and are switching at the same output frequency, then capacitive-load power consumption PL = CL×VCC2 ×fO×NSW where fO = output signal frequency, and CL = external (load) capacitance per output. When there are different loads and different output frequencies at all the outputs, the equation becomes PL = Σ(CLn ×fOn) ×VCC2 where Σ = sum of n different frequencies and loads at n different outputs, fOn = all different output frequencies at each output, numbered 1 through n (Hz), and CLn = all different load capacitances at each output, numbered 1 through n.
Thus dynamic power consumption (PD) is the sum of these two power consumptions:
where Cpd = power-consumption capacitance (F). Total power consumption is the sum of static and dynamic power consumption: Ptot = P(static)+P(dynamic). Cpd includes both internal parasitic capacitance (e.g., gate-to-source and gate-to-drain capacitance) and through-currents present while a device is switching and both n-channel and p-channel transistors are momentarily conducting.
Device manufacturers typically calculate Cpd by putting their device in a specified state of operation and measuring the dynamic ICC using a true RMS multimeter. Testing frequently takes place at an input frequency of 1 MHz so the contribution of the dc supply current can be ignored. The test frequency must be low enough to allow the outputs to switch from rail to rail. Consequently, devices with three-state outputs are typically measured at 10 MHz.
That said, it is clear from CMOS manufacturer app briefs that the power measurement process can be a bit tricky. The dynamic ICC depends heavily on through-currents present while a device is switching and both n-channel and p-channel transistors are momentarily conducting. While an input is switching, there is a brief period when both P-channel and N-channel transistors conduct, allowing through-current to flow from VCC to ground through the input stage. The amount of dynamic through-current measured is directly proportional to the amount of time the input signal is at some level other than VCC or ground.
Consequently, device manufacturers specify the rise and fall time of the input signal, also known as the edge rate or slew rate, during measurements of ICC. The typical specification is for an input edge rate of 1 nsec from 10% to 90% of the input signal. The implication here is that slower edge rates cause more through-currents and high power dissipation. All in all, if the real circuit generates input signals with slower edge rates, the power dissipation of the CMOS device could greatly exceed that specified in the datasheet.
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