IC testers handle Arm eMRAM compiler IP on Samsung 28-nm FDSOI process technology

A new IC test solution is optimized for the eMRAM (embedded Magnetoresistive Random Access Memory) compiler IP from Arm, built on Samsung Foundry’s 28-nm FDSOI process technology. The new eMRAM test solution is the result of a collaboration between Mentor and Arm. Mentor also has a long track record of working closely with Samsung on innovative test solutions for a broad array of highly innovative technologies such as eMRAM.

Unlike many traditional memory technologies, eMRAM is not fabricated with conventional silicon circuitry, so it requires new approaches and technologies for IC testing and quality assurance. Mentor is working with Arm to leverage industry-leading Tessent software Built-In Self-Test (BIST) Design-for-Testability (DFT) technologies for testing the next-generation of Arm eMRAM compiler IP in development.

“Markets such as automotive, artificial intelligence, and the Internet of Things require high demanding memory features of high density and low power, which have not been easily provided by the conventional memory solutions,” said JaeSeung Choi, Design Enablement team project leader at Samsung Electronics. “Embedded MRAM is expected to deliver much higher integration with lower power consumption, and this type of non-volatile memory is starting to attract attention as demand from advanced technology applications is steadily increasing.”

eMRAM delivers high-speed performance with the non-volatility of flash in a single, high-endurance device. However, despite these advantages, eMRAM presents new types of defects and test challenges due to the inherent probabilistic nature of the new physics and different failure modes.

Perfecting the DFT techniques for the new failure mechanisms introduced with eMRAM technology will require close cooperation across memory providers, foundries and EDA providers. Samsung is collaborating with Arm on a test chip to leverage actual silicon results to expand the new Memory BIST capabilities offered by Mentor.

Engineered to increase memory yield by combining spare resources and multi-bit ECC logic, the testing solution under development by Mentor and Arm involves the expansion of new Memory BIST hardware and test algorithms. Additionally, Mentor’s built-in, automated trimming functionality is expected to help ease mainstream adoption of eMRAM throughout the industry.

Mentor Graphics, a Siemens business, 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777, www.mentor.com/products/silicon-yield/memory_test/