by Faride Akretch, Technical Marketing Manager, Tektronix
Use an MSO to efficiently implement digital designs while verifying and debugging signals.
As electronic products become faster and more complex, they are harder to design, verify and debug. Extensive verification of these designs must be performed to ensure reliable product operation. When problems occur, it is critical to quickly obtain insight into their root cause to fix them. Many times, the fastest way to obtain insight into the root cause is by analyzing the analog and digital representations of a signal simultaneously using a mixed signal oscilloscope (MSO).
An MSO combines the functions of a digital oscilloscope with the basic functions of a 16-channel logic analyzer, including parallel/serial bus protocol decoding and triggering.
An MSO’s digital channels view a digital signal as either a logic high or logic low, just like a digital circuit views the signal. In short, as long as ringing, overshoot, and ground bounce do not cause logic transitions, these analog characteristics are not of concern to the MSO. Like a logic analyzer, an MSO uses a threshold voltage to determine if the signal is logic high or logic low. Adjusting channel threshold settings can be useful in debugging circuits with mixed logic families.
There are two major digital acquisition techniques. Timing acquisition is the first technique where the MSO samples the digital signal at uniformly spaced times determined by the MSO’s sample rate. At each sample point, the MSO stores the signal’s logic state and creates a timing diagram of the signal. The second digital acquisition technique is state acquisition. State acquisition defines special times when the digital signal’s logic state is valid and stable.
Logic analyzers provide both timing and state acquisitions. An MSO’s digital channels acquire signals similar to how a logic analyzer acquires signals in timing acquisition mode. Typically, the MSO decodes the timing acquisition into a clocked bus display and event table, which is similar to the logic analyzer’s state acquisition display.
Digital timing waveforms look similar to analog waveforms except only logic highs and lows are shown. Timing acquisition analyses often focus on determining logic values at specific points in time and measuring the time between edge transitions on one or more waveforms. Color-coded displays are used to make it easier to see which signal corresponds to which test point.
Two basic tasks should be undertaken to prepare a MSO for digital acquisition. First, the MSO digital channel thresholds need to be configured for the logic family being measured to ensure the correct logic level is acquired. Second, the analog channel’s skews need to be adjusted for accurate time correlation between the analog channels and the digital channels.
To align the analog channels with the digital channels, the 2.5 V position for CMOS analog waveforms are time aligned with the CMOS logic transitions. These waveforms occur at the 2.5 V threshold. For logic families with symmetrical voltage swings like CMOS, the threshold is shown at half of the 5 V signal amplitude. However, for logic families with asymmetrical voltage swings like TTL, you typically need to consult the component data sheet and define the threshold as halfway (TTL Vthreshold = 1.4 V) between the logic device’s maximum low-level input voltage (TTL VIL = 0.8 V) and minimum high-level input voltage (TTL VIH = 2.0 V) values. The analog channels skews should be checked when the analog probes are changed and the digital thresholds should be checked when measuring a different logic family.
Triggering on the unexpected
This example involves using an MSO to verify a TTL burst signal that contains eight positive pulses. The positive pulse width specification range is 23.2 ns to 25 ns with 26 ns to 27 ns between the pulses. The time between the bursts was not specified.
Figure 1 shows a single shot acquisition where the MSO triggered on the first pulse edge. Depending upon when the MSO single shot acquisition button was pushed, the MSO could have triggered on any of the other rising edges. The acquired signal has eight pulses, which comply with the specification. The first positive pulse width is 23.88 ns and the negative pulse width is 26.18 ns which are automatically measured. These values are within the specifications.
A more robust verification technique is to have the MSO check every pulse with its triggering capabilities. For example, the MSO can be set up to verify the TTL burst signal by measuring every positive pulse and triggering on non-conforming pulse widths smaller than 23.2 ns. The single shot acquisition mode can be used to stop the MSO after it triggers, allowing the non-conforming pulse to be analyzed.
In Figure 2, the MSO triggered on a non-conforming positive pulse less than 23.2 ns. Two errors were captured in this acquisition. The first error is that the seventh pulse is 3.636 ns wide, which is smaller than the 23.2 ns minimum specification. The second error is the missing eighth pulse. This is an example of using digital triggering to look for non-conforming digital signals. Also, in looking for non-conforming digital signals, the MSO trigger can be used to look for pulses greater than 25.6 ns. In this case, no problems were found.
The root cause of this error was a design flaw. The signal that controlled the gating of the pulses was asynchronous to the generation of the pulses and it occasionally varied in its gating duration. As a result, the internal gating signal intermittently chopped off the last pulse and clipped the seventh pulse.
This verification technique of triggering on errors can be used to monitor the signal for long durations, such as overnight or over the weekend, to provide even more rigorous verification of a design.
See the complete picture
In the next example, two Low-Voltage Positive Emitter-Coupled Logic (LVPECL) signals were verified. The 3.3 V LVPECL logic high is approximately 2.4 V and the logic low is approximately 1.6 V. Therefore, the MSO digital channels thresholds were set to 2.0 V.
Signal zero is a square wave with approximately 50 ns period and signal one is a square wave with approximately 90 ns period. There is no fixed time relationship between the signals. The same verification technique that was used in the previous TTL burst example was used to verify these LVPECL signals. To check for non-conforming signals, the MSO was configured to trigger-on a pulse width less than 22.4 ns. In Figure 3, the bottom digital signal glitch occurs at the same time that the rising edge of the top signal occurred, which could indicate a crosstalk problem.
With the MSO analog channels also connected to both LVPECL signals, the analog glitches also occur at the same time that the rising edges occur on the other signal. Most of these analog glitches are below the LVPECL logic threshold, but some of these glitches cross the logic threshold and are seen as logic errors such as the glitch on the top waveform at the left edge of the display.
By capturing and displaying the time-correlated signal’s digital and analog characteristics, the MSO provided insight into problems with the signal integrity of the digital signals. The root cause of these glitches were rising edge crosstalk between the two LVPECL signals. The LVPECL rising edge transitions were driven harder and faster than the falling edges. As a result, the rising edges created significantly more crosstalk than the falling edges. There was no indication of falling edge crosstalk in this acquisition.
Non-monotonic edges and setup/hold violations
The example looks at verification of a TTL 74F74 D-Flip-Flop. The D-Flip-Flop rising clock edge loads the D input into the Q output. In Figure 4, the D-Flip-Flop data input is the middle waveform and the Q output is the top waveform. The digital channels were labeled OUT, DATA and CLK to make it easy to identify each waveform.
The clock positive pulse width was 7.455 ns and the MSO trigger was configured to find non-conforming clock pulses less than 6.40 ns. Figure 4 shows that the MSO triggered on a 727.3 ps glitch on the clock signal just before the normal clock pulse. Looking at the analog signal in Figure 4 provides insight into the cause of the glitch. The rising clock edge was non monotonic. Using cursors, the clock voltage was determined to be 2 V in the middle of the glitch and moving the cursor approximately 500 ps to the right, the clock voltage drops to 1.76 V. This voltage drop caused the logic state to change from logic high to low for a short time before the clock signal voltage continued to increase.
The 74F74 specification is 0.8 VIL maximum low-level input voltage, and 2 VIH minimum high-level input voltage. A clock signal with slow rise time or non-monotonic operation between VIL and VIH can cause undefined D-Flip-Flop behavior. Based on this acquisition, the non-monotonic clock edge does not seem to be causing any problem. The non-monotonic clock edge was documented in the verification report and the next task is verifying the Q output operation.
The Q output should only change as a result of a change at the input and the change should only occur at the rising clock edge plus the D-Flip-Flop propagation delay. The clock has a fixed period of 20 ns. Therefore, the Q output should not have any pulses less than 20 ns wide because the Q output should only change at rising clock edges, which are 20 ns apart. The MSO was configured to trigger on a Q output pulse width less than 19.2 ns.
Figure 5 shows the MSO captured a Q output pulse width less than 19.2 ns, which is less than the clock period. Analysis of the waveforms show that the D input is high when the rising clock edge occurred. The Q output low-to-high transition is correct but the following high-to-low transition is an error in the D-Flip-Flop operation because the transition is unrelated to a rising clock edge.
When looking at the analog channel in Figure 5, the Q output analog signal started to increase but shortly thereafter it decreased. Notice the Q output analog signal did not reach the normal analog logic high level before it dropped back down. This typically is a metastable glitch caused by a setup/hold timing violation of the D input in regards to the clock edge.
At this point, the verification process identified three problems with the D-Flip-Flop operation and its signals. The first problem was a non-monotonic rising clock edge. The clock circuit needs to be redesigned to have a better rising edge. The second problem was the 74F74 not correctly working with D input setup times of 2 ns to 4.188 ns. This may be related to the poor rising clock edge or the 74F74 not meeting its specifications. The third problem was the D input setup/hold violation. The D input circuit needs to be redesigned so that it does not change during the clock edge setup/hold window.
Mixed signal oscilloscopes are invaluable to designers who verify the complex interaction of digital, analog and software in their designs. Providing basic logic analyzer function with the ease-of-use of an oscilloscope, they feature comprehensive tools including powerful digital triggering, high-resolution acquisition capability, and built-in analysis tools to quickly verify and debug digital circuits.