Protocol analyzers and jammers let you test and troubleshoot the performance of PCIe interconnects. From generation to generation, PCIe speeds double. Today’s protocols can be challenging to test and qualify. In addition, advanced applications such as the non-volatile memory express (NVMe) solid-state drive (SSD) memory protocol developed specifically for use with PCIe require sophisticated testing to ensure maximum performance. That’s where analyzers and jammers work in tandem.
This FAQ looks at how analyzers and jammers work individually and as teams, the different connectivity needs of standard vertical implementations versus horizontal PCIe implementations in high-density systems like servers, and how PCIe analyzers can work cooperatively with other analyzers to test bridges.
PCIe is designed for use with high-performance applications like servers, storage devices, graphics, and imaging. These high-performance systems must be reliable, and they must support interoperability. Those demands increase the challenge of adequately testing PCIe interfaces.
For example, NVMe enables systems to take advantage of the levels of parallelism in high-performance SSDs. Being optimized for use with PCIe reduces the I/O overhead and enables adding multiple long command queues with reduced latency.
Analyzers can provide detailed visibility into traffic flow, and they support advanced trace analysis. They use packet monitoring and recording to measure bus throughput rates and link performance. Triggering, error reporting, and analysis can help speed error identification and remediation. That’s all great for testing, but more is needed for troubleshooting. That’s where jammers come in.
A PCIe jammer is an inline error injection tool that can manipulate traffic in real-time and simulate an operational environment. Jammers can automate the implementation of predefined testing routines.
Analyzers and jammers are often supplied as matched sets. The jammer plugs between the device under test and the PCIe host system. A ribbon cable can connect the jammer to the analyzer, enabling the two pieces of equipment to work in unison. For example, the devices can cross-trigger each other, with the analyzer directing the jammer to inject an error signal and the jammer triggering the analyzer to start capturing the data stream for analysis (Figure 1).
The analyzer is often connected to a PC where various software packages reside to control specific testing routines and present the results. Jamming scenarios can include modification, replacement, insertion, and deletion of packets in the traffic between the PCIe root complex and the device being tested. Some jammers can insert correctable, uncorrectable, and fatal errors, and they can also insert bus errors and assert or de-assert commands on the PCIe sideband bus. Testing packages are available for various testing needs like standardized reliability, accessibility, and serviceability (RAS) testing.
Not all systems use vertical PCIe connectivity. High-density systems such as servers use horizontal insertion of PCIe devices. For those systems, a standard interposer can’t be used, and a horizontal connection is needed. Analyzers are also available that can synchronize operations with other high-speed serial bus analyzers to test and validate operations across bridges (Figure 2).
PCIe analyzers and jammers are important pieces of test equipment to ensure robust and reliable connectivity. They need to operate in a coordinated manner to implement thorough testing and troubleshooting of PCIe systems. Some PCIe analyzers are also designed to work with other types of protocol analyzers for testing the performance of bridges.